Semiconductor memory devices can store data and output the stored data on command. Semiconductor memory devices may be roughly categorized into random access memory (RAM) and read only memory (ROM) devices. A RAM device is typically a volatile memory device that loses its stored data at power-off, although some types of RAM devices are non-volatile. Examples of RAM devices include dynamic RAM, static RAM, and the like. The ROM device is a non-volatile memory device that can retain its stored data even at power-off. Examples of ROM devices include programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, and the like. Flash memories can be further classified into NAND-type flash memory and NOR-type flash memory depending on the kinds of logic gates used to implement the memory.
In general, a NAND flash memory may include a cell array, which includes a plurality of memory blocks. Each of the memory blocks may include a plurality of pages. A memory block is typically used as the basic unit for an erase operation, and a page is typically used as the basic unit for a read/write operation.
NAND flash memory devices have been successfully utilized in mobile communication terminals, portable media players, digital cameras, portable storage devices, and the like. In order to use a NAND flash memory device as a storage medium, it may be desirable to secure the integrity of data stored in the NAND flash memory device. However, a NAND flash memory can experience bit failures due to its physical characteristics. Thus, some NAND flash memory devices are configured to be able to detect and/or correct bits that have failed (i.e., “failed bits”). In order to detect/correct failed bits, an error correction code (ECC) circuit may be provided in the NAND flash memory device.
An ECC algorithm may be loaded onto the ECC circuit of the NAND flash memory. This may enable the NAND flash memory device to correct failed bits that may be generated during a read/write operation. Accordingly, it is possible to improve the reliability of a NAND flash memory through the use of error detection/correction circuitry.
In general, a number of packaged memory devices may be tested simultaneously to reduce the time required for testing. Since a test apparatus configured to simultaneously test packaged memory devices may have an error capture RAM that has a limited memory capacity, a compressed and/or summarized test result may be stored in the error capture RAM. According to this test scheme, although a memory block of a packaged memory device may have only one failed bit, the memory block will be considered to be a bad block. In this case, it may not be possible to detect the number of failed bits (i.e. a “failed bit number”) of a memory block that has been determined to be a bad block.
A software technique for individually counting failed bits at a test stage may be used to determine the number of failed bits. For example, it is possible to precisely measure a failed bit number for each memory device by storing test results corresponding to all memory cells in an error capture RAM. However, since the storage capacity of the error capture RAM may be limited, the number of memory devices to be tested at the same time may also be limited. This means that the time required to perform the test may be increased.
In methods of counting failed bits in a conventional NAND flash memory, a failed bit number can be detected by inputting expected data through input/output terminals and comparing the expected data with data read from a page of the flash memory. Such a method of generating a failed bit count is disclosed in U.S. patent publication No. 2002-0069381.
In a conventional method of counting failed bits, it may be possible to detect both the existence of a failed bit and the number of failed bits. However, it may not be possible to detect the position of the failed bits (i.e. a “failed bit position”) in the memory. In order to correct failed bits, the position of the failed bits must be determined by a tester. Further, since the sample data from a tester is input in predetermined units (e.g., byte or word units), a long time may be required to test failed bits.